SPI on SL808xT


#1

Inconsistent documentation:
The PTS (rev 7.0) lists SPI clock minimum 0.102 MHz and maximum 26MHz.
The ADL User Guide for SL808xT (version 3.0) sets a minimum SPI clock limit as 0.96MHz.

Missing data:
The SPI Waveforms section of the PTS does not indicate what delay there is between CS and CLK. Should indicate the delay for both dedicated SPI-CS and GPIO as CS.

Other missing data:
Delays between Opcode, Address and Data for adl_busRead/adl_busWrite.
That there is a delay between them is no problem, and is actually desired for our use, since the hardware that is being interfaced with needs time to prepare between each.

Other comments/questions:
Are there any plans to support full duplex operation (with associated api changes)?
5 SPI clock values is rather inflexible… Any plans to change this?
Is the hardware capable of slave mode operation and it’s just not supported by the software?


#2

Hi,

There are some issues with the PTS.PTS will be modified soon with new release.

Thanks.