SL8082T - SPI CLOCK speed setting 4 looks broken

S4_1_0_21AP R2371 CNSHZ-ED-XP0031 2014/11/27

The clock speed (Clock_Speed in example struct below) - works differently from the manual.

0 = 1MHz
1 = 5MHz
2 =10MHz
3 = 15.34MHz
4 =15.34MHz

From manual - > On SL808xT:
The Clk_Speed parameter corresponds to an index in the follow rate table:

0 = 0.96 MHz
1 = 4.8 MHz
2 = 9.6 MHz
3 = 15.36 MHz
4 = 26.33 MHz


typedef struct{
u32 Clk_Speed;
u32 Clk_Mode;
u32 ChipSelect;
u32 ChipSelectPolarity;
u32 LsbFirst;
adl_ioDefs_t GpioChipSelect;
u32 LoadSignal;
u32 DataLinesConf;
u32 MasterMode;
u32 BusySignal;
} adl_busSPISettings_t;

It is a Firmware bug which has been fixed in 7.53.1.A1 (currently in beta version).

Hi Susil

Many thanks

Is a list of bugs in the released FW available?
Is a FW release date for SL8 7.53.X available?


Not sure, but I think it may be released in a month or two. Check with your FAE or distributor to see if they can give you the beta release for evaluation.