WP77xx/WP76xx SPI minimum speed

IoT Modules WP Series
1

Hello Everyone,

I have low speed SPI slave peripheral, 2400 baud actually.
In the WP77/WP76 series specification I found that SPI1 master supported speed only from 960 kbps to 25 Mbps. In many other microcontrollers I used, was possible to set lower SPI speed than mentioned in documentation. Is it possible to set lower SPI speed here? Or just do not to try (because it will not work with guarantee)?

What about another approach? setup SPI to 960000 Hz as mentioned in the documentation, and make divider to provide 2400 Hz SPI clock to device. Then each bit to receive/send shall be represented by 400 bits with the same value. Anyone tried this? What maximum SPI master transaction length is supported?

With best regards, Sergey.

2

You need to make some test to see whether it works or not as this is out of the scope of specification.

You can refer to these sample code and modify the clock speed:

3

Minimum SPI frequency is 960000. It’s impossible to set lower value.
However, I see 22us inter-word delays as in “Spi clock interruption” topic. I investigated, that delay_usecs in spi transfer structure is always 0, so, it’s not the delay you mentioned in this topic. This delay is related to Qualcomm SPI bus master driver module.
In more recent kernels they have word_delay_usecs SPI transfer parameter, to be able to change this delay from user-space.
Do we have SPI configuration registers specification for WP77xx/WP76xx?

4

You have tried that???

No, i don’t have, you might need to contact distributor to get it

Btw, you can also have a look at ./kernel/drivers/spi/spi.c to see if there is any register to change that

5

Yes, I tried this. 960 kHz minimum, and 50 MHz maximum. Exactly as mentioned in the documentation.
I’m in doubt about this inter-word delay. It should not be by default. I found sierra,deassert-time set to 20 in the kernel device tree, but it’s related to SPI_CS de-assert, and cs_change is also set to 0 in all spidev calls.

6

Then seems what you are looking for is out of specification

7

But 20us inter-word delay is out of SPI specification as well.

8

Where is the spi specification you mentioned?

9

I meant common SPI specification. It should support continuous data block transfers, without slow-down delays.

10

Some spi slave might not care about this
Is your hardware being blocked?

11

My hardware SPI works at 2400 Hz. The difference between 960000 and 2400 is 400 times. I made generator to provide 2400 Hz SPI_CLK to device, synchronized with SPI_CLK from the WP77xx. Then, to transfer 1 bit to device, I should have 400 consequent bits with the same value in SPI buffer. 1 byte is represented by 400 bytes. And vice versa, for receiving of the data from device. For this approach SPI master should not have inter-word delays at all.

12

I tried to set “sierra,deassert-time” for spi1 to 0 value. Now inter-word delay is about 2 microseconds. In other words, approximately 2 periods of SPI_CLK. The question is why this parameter affects transaction with SPI_CS active and not switching.

13

See if this helps.
Here shows 24 clock pulse continuously

14

It’s absolutely different problem,
I’m using 8 or 32 bits per word, and transferring 400 bytes array at 960000 Hz. On the external device side it will be exactly 1 byte at 2400 Hz. Of course, this array should be properly encoded, to emulate waveform for 2400 Hz rate. 400 bytes in one SPI transaction.
What I see is that SPI_CS switching properly before the beginning of transaction, and after end of it. However, after each word (8 or 32 clock periods) SPI master making delay for 22 us (by default) or for 2 us (when spi1 sierra,deassert-time is set to 0 in kernel DTS). And during this delay SPI_MOSI is always set to 0 logic level. This blocks all.

15

So, probably, I need to switch to GPIO bit-banging to emulate low-speed SPI, using high resolution timer in Linux Kernel.

16

Yes, you can try this:

I remember I can generate some clock signal like 2000Hz with a GPIO pin.