Limitation of the flash R/W cycle


#1

Hi,

I would like to know the limitation of the flash R/W cycle.

I have searched in adl user guide document, but there is no mentation about this.

Any one help me to find out the above flash R/W cycle limitation.

Thanks & Regards,
Fazal M


#2

I think it mentions that there is a limit - but give no indication of what that might be! :unamused:

Usually, the limit is on erase cycles - not writing and certainly not reading.

I think that Open-AT manages “wear-levelling”… for the Flash and A&D Services :question:


#3

Hiya,

I’ve also asked about the FLASH endurance - and haven’t had an answer. I believe that I have seen something in one of the development docs, but can’t put my hands on it at the moment.

Can anyone confirm that Open-AT does wear-leveling on the Flash? I’ve asked my distributor this question - but no answer!

It’s quite important in my application.

ciao, Dave


#4

Hiya All.

Found a reference to Flash Erase Endurance in the Open AT 2.10 ADL User Guide. A note at the bottom of Page 89/415 says

(my emphasis).

Nothing explicit about wear levelling though.

ciao, Dave


#5

My information is that there is some kind of wear leveling implemented, altough i don’t know any details.

If you are so worried about the flash endurance, maybe you should look at the new “permanent RAM” feature of OS 7.2.