RC76xx power-up sequence and GPIO state

I need some details about the power up sequence and GPIO state for RC76xx modems.

The RC76xx technical guide indicates on the “POWER-UP SEQUENCE” section (4.1.1) :

“The host should not drive any signals to the module until the VGPIO raises up (approximately 100 ms after power ups). Before reaching the “Active” state, signals on the host port must be set to “floating, high impedance, or input pull-down”. This setting also applies when the module is in reset mode, during a firmware update, or during a power-off sequence.”

That means that even if GPIO has rised, I cannot drive TX, RTS and DTR inputs of the module UART1 (even with a pullup), I have to wait for the module to be in active state. But there is no chronogram that indicates how I know if the active state is entered and when I can drive these inputs. I guess that the CTS signal can be used (will rise shortly after VGPIO rise, and then return to low level to indicates UART port activation), but there is no chronogram about that (on the HL780x tech guide it is given precisely). Could you give me detailled timings during power up sequence ?

This constraint forces be to use a first translation buffer to convert the modem outputs (including CTS) to the host, and another translation buffer that drives the modem inputs (TX, RTS, DTR), and this buffer will be enabled only by the host only when the module has started.

Adding this buffer control signal independent of VGPIO complexifies my design. It would be much easier for me to drive these inputs with classic buffer powered by VGPIO, or even with a open drain buffer and a low value pull up resistor (4k7 for exemple) to VGPIO, but the module doc does not allow these topologies.

However, curiously, the schematic on the section 7.5 (serial link access for debug) shows pullups on TX and RTS inputs. And on the MangOH Red schematic (the WP family has the same constraint), the TX/RX/CTS/RTS signals are sharing the same buffer (FXMA108).

Can I drive the TX, RTS and DTR inputs with a high level signal as soon as VGPIO rises (i.e. using a buffer powered by VGPIO) ?

Thank you