Hi,
I just done a test using the parallel port to write LCD through FPGA. the FPGA using 8Mhz clock.
I test the performance between two adl_busDirectWrite, it take over 90us. 26Mhz MPU to 8MHz FPGA,
the lowest performace should be 125ns clock x 10 times (CS setup, access, hold, turnarround) = 1.25us,
But adl_busDirectWrite take 90us, almost 80 times as expected.
the code is as following,
adl_busDirectWrite (Parallel_Handle, Addr_Reg_Addr, WRITE_SIZE, &Addr);
for (i = 0; i < len; i++)
{
adl_busDirectWrite (Parallel_Handle, Data_Reg_Addr, WRITE_SIZE, &data[i]); }
}
could anyone can explain why ? or it’s Sierra bug?